This invention relates to programmable logic integrated circuit devices, and more particularly to the organization of various types of resources (e.g., logic, memory, and interconnection conductors) on such devices.
It is known to provide programmable logic integrated circuit devices with blocks of programmable logic, blocks of memory (e.g., random access memory (xe2x80x9cRAMxe2x80x9d) or read-only memory (xe2x80x9cROMxe2x80x9d)) that are accessible to the user, and programmable interconnection conductor resources for selectively conveying signals to, from, and between the logic and memory blocks (see, for example, Cliff et al. U.S. Pat. No. 5,550,782 and Cliff et al. U.S. Pat. No. 5,689,195, both of which are hereby incorporated by reference herein in their entireties). The logic blocks are programmable by the user to perform various logic functions desired by the user. The memory blocks may be used by the user to store and subsequently output data or to perform various logic functions desired by the user. The interconnection conductor resources are programmable by the user to make any of a wide range of connections between inputs of the device and inputs of the logic and memory blocks, between outputs of the logic and memory blocks and outputs of the device, and between outputs and inputs of the logic and memory blocks. Although each individual logic module (of which there may be several in each logic block) and memory block is typically able to perform only a relatively small logic or memory task, the interconnection conductor resources allow concatenation of these individual logic and memory tasks so that extremely complex functions can be performed if desired.
Improvements in integrated circuit fabrication technology are making it possible to make programmable logic devices with very large amounts of logic, memory, and interconnection conductor resources. Increasing the amounts of logic and memory on a programmable logic device has a tendency to call for more than a proportional increase in the amount of interconnection conductor resources provided. This is so because, at least in theory, it is desirable to be able to connect any inputs and outputs on the device to one another without other possibly desired connections being blocked or prevented. As the number of logic and memory blocks on the device increases, the number of inputs and outputs increases in approximately linear proportion. But the number of possibly desired connections between inputs and outputs tends to increase in a more exponential fashion. This can lead to excessive amounts of the total resources of the device being devoted to interconnection conductors and associated circuitry.
In view of the foregoing, it is an object of this invention to provide organizations for large programmable logic devices that help to reduce the need for excessive amounts of interconnection conductor resources on those devices.
It is a more particular object of this invention to provide arrangements for the logic and memory blocks on large programmable logic devices which facilitate provision of large amounts of anticipated interconnections on a xe2x80x9clocalxe2x80x9d basis, using relatively short interconnection conductors, so that the amount of more xe2x80x9cexpensivexe2x80x9d longer-length interconnection resources can be reduced, thereby helping to limit the fraction of overall device resources that must be devoted to interconnection resources.
These and other objects of the invention are accomplished in accordance with the principles of the invention by providing programmable logic devices having a plurality of super-regions (each including programmable logic and memory) disposed on the device in a two-dimensional array of intersecting rows and columns of such super-regions. Each super-region includes a plurality of regions of programmable logic and a region of memory. Each logic region includes a plurality of subregions of programmable logic. Each subregion is programmable to perform any of several relatively elementary logic functions on a plurality of input signals applied to that subregion in order to produce at least one subregion output signal. Each memory region has a plurality of memory inputs via which signals can be applied to the memory (e.g., for use in writing to or reading from the memory). Each memory region also has a plurality of outputs via which signals can be output by the memory.
A first level of interconnection conductor resources is provided within each super-region for communicating between adjacent subregions in that super-region. (In some cases the first level interconnection conductors also allow communication between a subregion and a memory region if such a memory region is adjacent to those first level interconnection resources.) A second level of interconnection conductor resources is provided within each super-region for longer-distance communication within that super-region (e.g., between logic regions and memory regions in the super-region). A third level of interconnection conductor resources is provided on the device for communication to, from, and between the super-regions.
Inclusion of a memory region in each super-region helps reduce the need to use the third level of interconnection conductor resources. For example, each memory region can work with the logic regions of the super-region that includes that memory region by using only the first and second level interconnection conductor resources of that super-region. This is illustrative of the ways in which the programmable logic device organizations (xe2x80x9carchitecturesxe2x80x9d) of this invention help reduce or at least hold down overall interconnection resource requirements on large programmable logic devices.
Further features of the invention, its nature and various advantages will be more apparent from the accompanying drawings and the following detailed description of the preferred embodiments.